1. Field of the Invention
The present invention relates to implementing a programmable chip using a reduced operand select logic. In one example, the present invention relates to methods and apparatus for efficiently implementing processor having processing blocks using reduced multiplexing circuitry.
2. Description of Related Art
Conventional processors such as Digital Signal Processing (DSP) processors include processing blocks that obtain data by accessing registers. Individual register data values are selected using multiplexing circuitry associated with operand select logic. For example, processing blocks such as arithmetic logic units (ALUs) and multiply accumulate units (MACs) each take two register values as input during a particular clock cycle. A register bank can include, for example, 16 data registers. A processor having an ALU and a MAC would select 4 values from the data registers as input during a particular clock cycle using multiplexers.
Typically, the ALU and MAC would use multiplexing circuitry including 4×16:1 multiplexers to select 4 data values from data registers during a particular cycle. However, using such a set of multiplexers can be inefficient. Mechanisms for using more efficient multiplexing circuitry are relatively limited.
Consequently, it is desirable to provide improved methods and apparatus for reducing the amount of resource allocated for handling selection logic in a processor.